CXL Consortium Showcases First Public Demonstrations of Compute Express Link Technology at SC21

BEAVERTON, Ore., Nov. 15, 2021 — The CXL Consortium, an trade requirements physique devoted to advancing Compute Categorical Hyperlink (CXL) expertise, will showcase rising momentum for CXL expertise at Supercomputing (SC21), happening at America’s Middle in St. Louis, Missouri and nearly November 15-18. The CXL specification permits a high-speed, environment friendly interconnect between the CPU and platform enhancements and workload accelerators, akin to GPUs, FPGAs and different purpose-built accelerator options. 12 corporations shall be demonstrating their CXL options in the course of the present, together with multi-vendor demos that spotlight the rising CXL ecosystem.

CXL logo“These CXL demonstrations are an essential milestone for our group,” stated Barry McAuliffe, president, CXL Consortium. “When the CXL Consortium was based two years in the past, we had a imaginative and prescient to ship to the trade an open commonplace that might speed up next-generation information heart efficiency. That imaginative and prescient has now turn out to be actuality as a number of member corporations are delivering CXL options showcasing interoperability between distributors and enabling a brand new ecosystem for high-performance, heterogeneous computing.”

“We’re excited that our members have come collectively to showcase the primary reside expertise demonstrations of CXL at SC21, together with options that includes reminiscence growth, end-point help, reminiscence disaggregation and extra,” stated Glenn Ward and Kurt Lender, MWG Co-Chairs, CXL Consortium. “The expertise demonstrations will characteristic the primary CXL {hardware} and can spotlight use circumstances within the trade that may profit from CXL’s excessive pace, low latency, cache coherent interconnect.”

CXL Demos at SC’21:

  • Elastics.Cloud – Proof of Idea: Reminiscence Disaggregation Native, Expanded, and Distant Reminiscence: The demo video introduces its reminiscence disaggregation and pooling resolution based mostly on the rising CXL commonplace. Its Sensible Interconnect resolution will additional allow the sharing of reminiscence in heterogeneous compute environments, whereas enhancing the efficiency required by essentially the most demanding workloads. Optimized for higher part utilization and enhanced efficiency, will allow performance throughout a tiered information heart mannequin, whereas reducing complete price of possession at scale.
  • Cadence IP for CXL Interop Demonstration: On this video demo, Cadence will show its Endpoint Controller IP for CXL 2.0 interoperating with a CXL Host Server platform. This video will present a profitable CXL linkup with a protocol analyzer, configuration area learn and write, and reminiscence learn and write.
  • GigaIO – The Way forward for Composability with CXL: Earlier than CXL, the whole server may very well be disaggregated into swimming pools of sources (CPU, storage, accelerators), apart from reminiscence. This video traces the journey and descriptions the brand new capabilities CXL 1.0 and a couple of.0 will add to the composable area, specifically, coherent reminiscence pooling and reminiscence sharing as a part of a disaggregated information heart rack.
  • IntelliProp – CXL Cloth Adaptor Bridge Demo: Demonstration of CXL Cloth Adaptor and Cloth Hooked up reminiscence which is managed utilizing a prototype Cloth Supervisor software program. The demonstration showcases the power to dynamically bind material connected sources to a CXL Host Node utilizing in-band administration over CXL and material protocols.
  • Meta – CXL Sort 3 Reminiscence Gadget Demo
  • Montage Expertise MXC + Retimer Video: The demo exhibits a FPGA Base POC of a CXL Type3 reminiscence expander controller (MXC) supporting CXL.mem and protocols. It integrates a CXL controller, a DDR4/5 reminiscence controller & a RISC-V micro-processor, and helps interfaces together with SMBus for Host, I3C/I2C for media facet and an SPI interface for exterior SPI flash. A PCIe 5.0 retimer is used to safe the hyperlink finances to fulfill the difficult sign integrity necessities for lengthy PCIe 5.0 channel comprising PCB, connector and cable. It makes use of superior sign conditioning methods to compensate for the channel attenuation and take away the impacts of assorted jitter sources.
  • Multi-Vendor Full CXL System Demonstration between Astera Labs, Intel, and Synopsys: This multi-vendor demonstration exhibits strong CXL interoperability between an Intel Sapphire Rapids CPU, Astera Labs’ Solstice 3U Riser Card with two Aries CXL Sensible Retimers, and the Synopsys DesignWare CXL Controller IP, displaying profitable transmission of, CXL.cache, and CXL.mem transactions.
  • Rambus – Demonstration of a CXL Interconnect on a FPGA-based Design: This video demonstrates CXL.mem learn/write accesses to Host-managed Gadget Reminiscence (HDM) between an Intel Host CPU and the Rambus CXL 2.0 Gadget Controller carried out in FPGA. The demonstration setup options Intel’s Pre-Manufacturing Xeon processor as a number, related to an FPGA board instantiating Rambus’ CXL 2.0 Controller and CXL.mem check design.
  • Samsung – Purposeful Integration of SAP HANA In-Reminiscence-Database on Samsung’s CXL Reminiscence Expander: Samsung Reminiscence Expander is a brand new kind of reminiscence system that helps CXL.mem protocol over PCIe slot. The top-to-end integration validates CXL ecosystem from OS, Linux kernel, CXL system driver, CXL.mem transactions and CXL hyperlink protocol. Samsung’s Reminiscence Answer Lab will apply this key expertise to resolve challenges of scaling of reminiscence and compute for its prospects.
  • Synopsys – Demonstration of DesignWare CXL IP: This demonstration, an entire CXL end-to-end connection, exhibits profitable information switch between Synopsys’ DesignWare CXL Root Complicated and Endpoint Controller IP options with full pace hint and evaluation supplied by a Teledyne LeCroy CXL Analyzer.
  • Teledyne LeCroy – CXL Dwell Site visitors Demonstration: This demo exhibits Synopsys DesignWare CXL Root Complicated IP interoperating with Synopsys DesignWare CXL Endpoint IP, utilizing a Teledyne LeCroy CXL Analyzer to seize the information and confirm habits.
  • Teledyne LeCroy – CXL Compliance Demonstration: This can be a demonstration of the Teledyne LeCroy Summit T516 Protocol Analyzer and Summit Z516 Protocol Exerciser working CXL 2.0 Compliance exams. This makes use of the Teledyne LeCroy LinkExpert software program to automate the whole course of.

CXL Presentation at SC’21

The CXL Consortium will even take part in a Birds of a Feather session “CXL Consortium, Gen-Z Consortium™, SNIA and End-Users – Is Disaggregation of Systems the Future?” on November 17 from 12:15-1:15 pm CST in Location 225-226 and on-line. The panel of specialists will focus on how the disaggregation of programs and protracted reminiscence are vital to the trade and is being enabled by the organizations’ applied sciences.

To schedule a gathering with a CXL consultant throughout SC21, contact

In regards to the CXL Consortium

The CXL Consortium is an trade requirements physique devoted to advancing Compute Categorical Hyperlink (CXL) expertise. CXL is a high-speed interconnect providing coherency and reminiscence semantics utilizing high-bandwidth, low-latency connectivity between the host processor and gadgets akin to accelerators, reminiscence buffers, and good I/O gadgets. For extra data or to affix, go to

Supply: CXL Consortium

Source link

Leave a Reply

Your email address will not be published. Required fields are marked *

Previous post Business Inclusion Office shares local success story
Next post Liverpool taxi bomb prompts U.K. to raise terrorism threat level